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3 - The Status Register
The status register is somewhat of a catchall for the system, containing flags, system settings, and indexes:
From other chips, flags like carry (C), overflow (V), zero (Z), and sign (S) will appear familiar, and operate the same. Other flags, such as the interrupt disable (I), vector high (VH), supervisor mode (SM) and exception disable (E) are beyond the scope of this article (and the majority of user programming), as is the alternate bank selector (ABS) and bank selection bits (BS0 and BS1). However, two unusual flags do need to be dealt with in order to program effectively - the instruction decode flag (K) and the RPTR index.
The K flag enables the 256-code maximum in a one-byte instruction set to be exceeded. When set, a particular code will mean a branch; when clear, it isn't. As an example, the hex byte code B6 is 'pop r6' (copy register r6's contents from the stack) when the K flag is clear, but when set it is interpreted as 'bne' (branch if not equal). Lest you worry about the state of the K flag while programming, it is cleared after almost every instruction, and set after only one - 'ldt' (LoaD to T register). Although a little confusing at first, it boils down to one simple rule: always perform a ldt immediately before a conditional branch. Note that only conditional branches are included, and so 'bra' (unconditional branch), 'jsr' (jump subroutine), 'jmp' (jump), and 'bsr' (branch subroutine) do not need this.
The R0 through R3 status bits are collectively known as the RPTR index. It can be set to any of 16 values, and so refers to any register in the current bank. Various commands use it to select the register for the current operation. For instance, 'and rp' will perform a bitwise AND between the t register and the register indexed by the RPTR value, placing the result in t afterwards.
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